High-dielectric sheet, a printed circuit board having the high-dielectric sheet and production methods thereof

ABSTRACT

A method of producing a capacitor for a printed circuit board includes producing high-dielectric sheets and selecting ones of the high-dielectric sheets, which are substantially free from a defect after the heat process. Each of the high-dielectric sheets is produced by providing a first electrode, forming a first sputter film on the first electrode, forming an intermediate layer on the first sputter film by calcining a sol-gel film, forming a second sputter film on the intermediate layer, and providing a second electrode on the second sputter film. The high-dielectric sheets are subjected to a heat process in which the high-dielectric sheets are subjected to a first temperature at least once and a second temperature higher than the first temperature at least once.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of and claims the benefit of priorityfrom U.S. application Ser. No. 11/580,927, filed Oct. 16, 2006, which isbased upon and claims the benefit of priority to prior Japanese PatentApplication No. 2005-300319, filed Oct. 14, 2005. The contents of eachof the above are incorporated herein by reference in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to a high-dielectric sheet, a printedcircuit board having the high-dielectric sheet, and methods of producingthe high-dielectric sheet and printed circuit board.

2. Discussion of the Background

A high-dielectric sheet is used as a thin-film capacitor provided insidea printed circuit board (herein after referred to as “PCB”). JapaneseUnexamined Patent Publication 2005-191559 describes a method ofproducing a high-dielectric sheet. In this method, a 1.2 μm-thickhigh-dielectric layer is formed on a copper foil by repeating severaltimes a process in which a mixed solution of diethoxy barium andtitanium bitetraisopropoxide is hydrolyzed to make a sol-gel solution,which is spincoated, dried and calcined on the copper foil. Then, acopper foil is formed on the high-dielectric layer by vacuum deposition.The above reference also discusses a method for forming ahigh-dielectric layer by sputtering using barium titanate as a targetmaterial.

However, in this method, when a high-dielectric layer is formed by usinga sol-gel solution, pinholes may occur after organic materials orsolvents are decomposed or evaporate during the process of forming thehigh-dielectric layer. Such pinholes are unwelcome, since they maybecome the starting points of cracks. Also, plating liquids may seepinto those pinholes when plating a metal foil on the high-dielectriclayer, thereby forming a conductor running through the high-dielectriclayer and potentially causing short-circuits. Furthermore, when ahigh-dielectric layer is formed by sputtering, pits (hollows) may occuron the surface. Such pits are not welcome, since they may also becomethe starting points of cracks in the high-dielectric layer. It is thusdesired to produce a high-dielectric layer by a method which does notproduce cracks in the high-dielectric layer and short-circuits betweenelectrodes. The contents of the above publication are hereinincorporated by reference in their entirety.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, a method of producinga high-dielectric sheet for a printed circuit board, includes providinga first electrode, forming a first sputter film on the first electrode,forming an intermediate layer on the first sputter film by calcining asol-gel film, forming a second sputter film on the intermediate layer,and providing a second electrode on the second sputter film.

According to another aspect of the present invention, a method ofproducing a capacitor for a printed circuit board, includes producingplural high-dielectric sheets, each of the high-dielectric sheets beingproduced by providing a first electrode, forming a first sputter film onthe first electrode, forming an intermediate layer on the first sputterfilm by calcining a sol-gel film, forming a second sputter film on theintermediate layer, and providing a second electrode on the secondsputter film, and subjecting the high-dielectric sheets to a process inwhich the high-dielectric sheets are subjected to a first temperature atleast once and a second temperature higher than the first temperature atleast once, and selecting ones of the high-dielectric sheets, which aresubstantially free from a defect after the heat process.

According to yet another aspect of the present invention, a method ofproducing a printed circuit board, includes providing a core substrate,and providing a capacitor over the core substrate, the capacitor beingproduced by providing a first electrode, forming a first sputter film onthe first electrode, forming an intermediate layer on the first sputterfilm by calcining a sol-gel film, forming a second sputter film on theintermediate layer, and providing a second electrode on the secondsputter film.

According to yet another aspect of the present invention, ahigh-dielectric sheet for a printed circuit board, includes a firstelectrode, a first sputter film formed on the first electrode, anintermediate layer formed on the first sputter film by calcining asol-gel film, a second sputter film formed on the intermediate layer,and a second electrode provided on the second sputter film.

According to yet another aspect of the present invention, a printedcircuit board includes a core substrate, and a capacitor provided overthe core substrate, the capacitor having a first electrode, a firstsputter film formed on the first electrode, an intermediate layer formedon the first sputter film by calcining a sol-gel film, a second sputterfilm formed on the intermediate layer, and a second electrode providedon the second sputter film.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the invention and many of the attendantadvantages thereof will be readily obtained as the same becomes betterunderstood by reference to the following detailed description whenconsidered in connection with the accompanying drawings, wherein:

FIG. 1 is a plan view of a multilayered PCB according to one embodimentof the present invention;

FIG. 2 is a cross-sectional view showing a part of the multilayered PCB;

FIG. 3 is a perspective view of a thin-film capacitor in themultilayered PCB;

FIGS. 4( a)-4(d) are cross-sectional views of a multilayered PCB beingproduced by a method according to one embodiment of the presentinvention;

FIGS. 5( a)-5(e) are cross-sectional views of a high-dielectric sheetbeing produced by a method according to one embodiment of the presentinvention;

FIGS. 6( a) and 6(b) are cross-sectional views of the multilayered PCBunder production after the steps shown in FIGS. 4( a)-4(d);

FIGS. 7( a)-7(d) are cross-sectional views of the multilayered PCB underproduction after the steps shown in FIGS. 6( a) and 6(b);

FIGS. 8( a)-8(c) are cross-sectional views of the multilayered PCB underproduction after the steps shown in FIGS. 7( a)-7(d); and

FIG. 9 is a schematic illustration of multilayered PCB showingconnections between pads and lines.

DESCRIPTION OF THE EMBODIMENTS

The embodiments will now be described with reference to the accompanyingdrawings, wherein like reference numerals designate corresponding oridentical elements throughout the various drawings.

FIG. 1 is a plan view of a multilayered PCB according to one embodimentof the present invention. Referring to FIG. 1, a multilayered PCB 10 hasa mounting part 60 on which a semiconductor component 70 is mounted. Inthe mounting part 60, ground pads 61, power source pads 62 and signalpads 63 are provided. The ground pads 61 are used for connection to aground line which grounds the semiconductor element 70. The power sourcepads 62 are for connection to a power source line which supplies anelectrical potential from a power source to a semiconductor element 70.The signal pads 63 are provided for connection to a signal line whichinputs and outputs signals to and from the semiconductor element 70.According to the present embodiment, ground pads 61 and power sourcepads 62 are positioned either in a lattice-like or zigzag pattern aroundthe center of the mounting part 60, and signal pads 63 are positionedaround those pads in a lattice-like or zigzag pattern or at random. Thetotal number of pads on mounting part 60 is 1,000-30,000.

FIG. 9 is a schematic illustration of multilayered PCB 10 showingconnections between pads and lines. As shown in FIG. 9, multilayered PCB10 has external terminals located on the surface opposite to mountingpart 60. Specifically, an external ground terminal 81, an external powersource terminal 82 and external signal terminals 83 are provided andconnected with ground pads 61, power source pads 62 and signal pads 63through a ground line 71, a power source line 72 and signal lines 73,respectively. The signal lines 73 are provided independently from theground line 71 and power source line 72 inside multilayered PCB 10. Thepower source line 72 is connected to an upper electrode 42 of athin-film capacitor 40 (see FIG. 2), and the ground line 71 is connectedto a lower electrode 41 of the thin-film capacitor 40.

FIG. 2 is a cross-sectional view of a part of the multilayered PCB 10.As shown in FIG. 2, multilayered PCB 10 has a core substrate 20, abuild-up part 30 and the thin-film capacitor 40. The thin-film capacitor40 is formed above core substrate 20 with an insulation layer 26provided therebetween. The build-up part 30 is formed above thin-filmcapacitor 40, and the mounting part 60 is formed on the topmost layer ofbuild-up part 30. Each of ground pads 61, power source pads 62 andsignal pads 63 provided in mounting part 60 is electrically connected toconductive layers (BU conductive layers) 32 which are wiring patternsformed inside build-up part 30. Core substrate 20 has conductive layers22 and a through-hole conductor 24. Conductive layers 22 are made ofcopper and formed on the top and bottom surfaces of a core substratebody 21, which is made of BT (bismaleimide-triazine) resin or glassepoxy substrate or the like. The through-hole conductor 24 is made ofcopper and provided on the inner surface of a through-hole whichvertically passes through core substrate body 21. Conductive layers 22are electrically connected to each other via through-hole conductor 24.

FIG. 3 is a perspective view of the thin-film capacitor 40 providedinside the multilayered PCB 10. As shown in FIGS. 2 and 3, thin-filmcapacitor 40 has a high-dielectric layer 43, a lower electrode 41 and anupper electrode 42. Lower electrode 41 and upper electrode 42 sandwichhigh-dielectric layer 43 which is made of a ceramic-type high-dielectricmaterial produced by calcining high-dielectric material at a hightemperature. Lower electrode 41 and upper electrode 42 are made ofnickel and copper, respectively.

As illustrated in FIG. 9, lower electrode 41 is electrically connectedto ground pads 61 in mounting part 60, while upper electrode 42 iselectrically connected to power source pads 62 in mounting part 60.Therefore, lower electrode 41 and upper electrode 42 are connectedrespectively to the ground line 71 and power source line 72 ofsemiconductor element 70 mounted on mounting part 60.

Referring back to FIG. 2, lower electrode 41 is a plane pattern formedbelow high-dielectric layer 43, and has a through-hole (41 a) whichallows an upper via-hole conductor 48 to vertically pass through withoutmaking contact. Upper via-hole conductor 48 electrically connects theupper electrode 42 with a power source conductive layer (22P), which isone of the conductive layers 22 on core substrate 20. Lower electrode 41may have a through-hole for each signal line to pass through lowerelectrode 41 without contact. However, it is preferred that each signalline be formed outside lower electrode 41 (see FIG. 9). Upper electrode42 is a plane pattern formed on top of high-dielectric layer 43, and hasa through-hole (42 a) which allows a lower via-hole conductor 45 to passthrough upper electrode 42 without making contact. Lower via-holeconductor 45 electrically connects lower electrode 41 with a groundconductive layer (22G), which is one of the conductive layers 22 on coresubstrate 20. Upper electrode 42 may have a through-hole for each signalline to vertically pass through without contact. However, it ispreferable that each signal line be formed outside upper electrode 42(see FIG. 9). High-dielectric layer 43 has three layers comprised ofceramic film, and these films are made of one or more metal oxidesincluding BaTiO₃, SrTiO₃, TaO₃, Ta₂O₅, PZT, PLZT, PNZT, PCZT and PSZT,and the total thickness of the high-dielectric layer 43 is in the rangeof 0.4-3 μm. As shown in FIG. 3, the three ceramic films, that is, afirst sputter film (43 a), an intermediate layer (43 b) and a secondsputter film (43 c) are laminated in this order from the side of lowerelectrode 41. First sputter film (43 a) and second sputter film (43 c)are formed by a sputtering process, and intermediate layer (43 b) isformed by calcining a sol-gel film. The individual thickness of firstsputter film (43 a) and second sputter film (43 c) is 0.1 μm or greater,and the intermediate layer (43 b) is thicker than both first sputterfilm (43 a) and second sputter film (43 c).

As shown in FIG. 2, build-up part 30 is formed above thin-film capacitor40 by alternately laminating build-up part insulation layers (BUinsulation layers) 36 and BU conductive layers 32. Each BU conductivelayer 32 is comprised of one or more conductive circuits provided on theBU insulation layer 36. BU conductive layers 32, which verticallysandwich BU insulation layers 36, are electrically connected to eachother through a BU via-hole conductor 34. BU conductive layers 32 arealso electrically connected to upper electrode 42 of thin-film capacitor40 through BU via-hole conductor 34. As BU part 30 is made thinner, BUconductive layer 32 is formed thinner than lower electrode 41. Themounting part 60 is formed on the topmost layer of the BU part 30.

BU part 30 as described above may be formed by, for example, asubtractive or additive process (including semi-additive orfull-additive processes). Specifically, a resin insulation sheet isfirst laminated on top and bottom surfaces of core substrate 20 to formBU insulation layers 36 (having Young's modulus of, for example, 2-7GPa, at room temperature). The resin sheet used above is made of adenatured epoxy type resin, polyphenylene ether type resin, polyimidetype resin, cyano ester type resin, or the like, and its thickness is inthe approximate range of 20-80 μm. Inorganic materials such as silica,alumina, zirconia, or the like, may be dispersed in such a resin sheet.Next, through-holes are formed in the above-laminated resin sheet byusing a CO₂ gas laser, UV laser, YAG laser, excimer laser, or the like,then the surfaces of the resin sheets and the inner surfaces of thethrough-holes are plated with electroless copper to make conductivelayers. A plating resist is formed in areas on the conductive layers,and electrolytic copper plating is applied except the areas where theplating resist is formed. BU conductive layers 32 are formed after theelectroless copper plating provided under the resist is removed with anetching solution. The inner surfaces of the through-hole become BUvia-hole conductors 34. The above process is repeated to form build-uppart 30. In the present embodiment, lower electrode 41 of thin-filmcapacitor 40 is thicker than BU conductive layer 32.

The above-described multilayered PCB 10 has the following use, forinstance. First, semiconductor element 70, having solder bumps on itsbottom surface, is installed on mounting part 60. During the mountingprocedure, ground, power source and signal terminals of semiconductorelement 70 are brought into contact respectively with ground pads 61,power source pads 62, and signal pads 63 of mounting part 60, andsoldered by a reflow process. Then, multilayered PCB 10 is installed onanother PCB such as a motherboard. Before the installment, solder bumpsare formed on a pad provided on the bottom surface of the multilayeredPCB 10. The pad is connected to the corresponding pad of another PCB bya reflow process. Because thin-film capacitor 40 provided inmultilayered PCB 10 has high-dielectric layer 43 made ofhigh-permittivity ceramic, and because lower electrode 41 and upperelectrode 42 are large plane patterns (may include partially openareas), the thin-film capacitor 40 has a larger capacitance. Thus, thethin-film capacitor 40 produces a sufficient decoupling effect, therebyreducing the risk of lower power supply to a transistor of semiconductorelement (IC) 70 provided on mounting part 60. If necessary,chip-capacitors may be installed around mounting part 60 of multilayeredPCB 10.

FIGS. 4( a)-4(d) are cross-sectional views illustrating production of amultilayered PCB 10 by a method according to one embodiment of thepresent invention. Referring to FIGS. 4( a)-4(d), a manufacturingprocess of multilayered PCB 10 of the present embodiment is described.First, as shown in FIG. 4( a), a thermosetting insulation film (ABF-45SHmade by Ajinomoto Fine-Techno Co., Ltd.) is laminated on core substrate20 by using a vacuum laminator under conditions calling for atemperature range of 50-150° C. and a pressure range of 0.5-1.5 MPa.This thermosetting insulation film becomes an insulation layer 26 underthin-film capacitor 40 illustrated in FIG. 2. Then, a high-dielectricsheet 420 comprised of a high-dielectric layer 423 sandwiched between anickel foil 421 and a copper foil 422 is attached onto the thermosettinginsulation film by using a vacuum laminator under conditions calling fora temperature range of 50-150° C. and a pressure range of 0.5-1.5 MPa,then dried for an hour at 150° C. (see FIG. 4( b)). Through thisprocess, the thermosetting resin film is hardened and becomes aninterlayer insulation layer 410. Nickel foil 421 and copper foil 422 ofhigh-dielectric sheet 420 used in the above lamination process are planepatterns without circuit patterns. However, nickel foil 421 may belaminated after etching out areas which will not be used later, forexample, those areas to become through-holes (41 a).

FIGS. 5( a)-5(e) are cross-sectional views illustrating production ofthe high-dielectric sheet 420. Referring to FIGS. 5( a)-5(e), amanufacturing process of high-dielectric sheet 420 is described. First,nickel foil 421 (an electrode) with an approximate thickness of 100 μmis prepared (see FIG. 5( a)) and heated at a temperature in the range of400-700° C. (550° C. in the present embodiment). This heating procedureenhances crystallinity of high-dielectric layer 423 formed on nickelfoil 421. After nickel foil 421 is heated, its surface is polished tomake the nickel foil approximately 90 μm thick. A first sputter film(423 a) is formed on nickel foil 421 (see FIG. 5( b)). Morespecifically, a sputtering target of BaTiOx (made by Japan Pure ChemicalCo., Ltd.) is furnished in a magnetron-sputtering apparatus (made byCanon Anelva Corporation, serial number L-332S-FH), and sputtering isconducted by using a DC or AC power source and gas mainly includingargon and oxygen at a pressure in the range of 3-10 mTorr. The oxygenlevel in the sputtering gas may be in the range of 10-90% by volume,preferably 45-55% by volume. Gas with an oxygen level 50% by volume isused in the present embodiment. RF power range is 2-5 W/cm² and asputtering pressure range is 0.5-2 Pa. A 0.25 μm-thick first sputterfilm (423 a) is formed. Since first sputter film (423 a) is thinner,even if pits occur on its surface, they are smaller and shallower.

An intermediate layer (423 b) is then formed on first sputter film (423a) (see FIG. 5( c)) by the following process. Specifically, diethoxybarium and titanium bitetraisopropoxide are weighed in a dry nitrogenatmosphere to prepare a solution with a concentration of 1.0 mol/literin a mixed solvent of dehydrated methanol and 2-methoxyethanol (volumeratio 3:2). Then, the solution is blended for three days in a nitrogenatmosphere at room temperature to prepare a solution containing abarium-titanium alkoxide precursor composition. Decarbonated water issprayed at a speed of 0.5 microliter/minute in an atmospheric nitrogencurrent to hydrolyze the precursor composition solution while blendingit at a constant temperature of 0° C. until it finally becomes a sol-gelsolution. The sol-gel solution is filtered through a 0.2-micron filterto remove precipitates. The filtered solution is then spincoated to forma sol-gel film on first sputter film (423 a) at a speed of 1500 rpm for1 minute. The substrate after the spincoating is dried for 3 minutes ona hot plate at a constant temperature of 150° C., then put in anelectric oven having a constant temperature of 850° C. to calcine thesol-gel film for 15 minutes. The viscosity of the solution is adjustedso that a layer thickness obtained after the spincoat/dry/calcine cyclebecomes 0.03 μm. After repeating 10 spincoat/dry/calcine cycles, a 0.3μm-thick intermediate layer (423 b) is formed. Pits on the surface offirst sputter film (423 a) are filled with the sol-gel solution when thesol-gel film is formed.

Next, second sputter film (423 c) is formed on intermediate layer (423b) (see FIG. 5( d)). To form a 0.15 μm-thick second sputter film (423c), the same magnetron sputtering apparatus is used as in the formationof first sputter film (423 a). At this stage, high-dielectric layer 423with a total film thickness of 0.7 μm is formed on nickel foil 421.Since second sputter film (423 c) is thinner, even if pits occur on itssurface, they are smaller and shallower. Intermediate layer (423 b) issandwiched between first and second sputter films (423 a) and (423 c).

Following the above process, a copper layer is formed on high-dielectriclayer 423 by electroless plating. Copper foil 422 (opposite electrode)is formed by, for example, electrolytically plating another copper layerof approximate thickness 10 μm on top of the above copper layer.Accordingly, high-dielectric sheet 420 is formed. After repeating 20times a cycle where high-dielectric sheet 420 is left for 5 minutes at atemperature of −55° C. and then left for 5 minutes at 125° C., a sheetfree of defects such as cracks is used for the next process. Thedielectric characteristics of the high-dielectric sheet obtainedaccording to the above-described procedures are measured usingIMPEDANCE/GAIN-PHASE ANALYZER (made by Hewlett-Packard DevelopmentCompany, L.P., product name 4194A) under conditions calling for afrequency of 1 Hz, a temperature of 25° C. and an OSC level of 1V. Inone example, the specific dielectric constant was 1300. In the methoddescribed above, the first sputter film, intermediate layer and secondsputter film of the high-dielectric layer are all made of bariumtitanate. However, any of the following may be used: strontium titanate(SrTiO₃), tantalum oxides (TaO₃, Ta₂O₅), lead zirconate titanate (PZT),lead lanthanum zirconate titanate (PLZT), lead niobium zirconatetitanate (PNZT), lead calcium zirconate titanate (PCZT) and leadstrontium zirconate titanate (PSZT). Also, the first sputter film,intermediate layer and second sputter film may be made of the samematerial or different materials.

Referring back to FIGS. 4( a)-4(d), through-holes 431 and 432 are formedby laser beams at predetermined positions in high-dielectric sheet 420,laminated on the unfinished substrate (see FIG. 4( c)). Through-hole 431is formed on dielectric sheet 420 at the opposite position to groundconductive layer (22G), which is one of the conductive layers 22 on coresubstrate 20. Through-hole 431 penetrates copper foil 422 andhigh-dielectric layer 423 and reaches the top surface of nickel foil421. Through-hole 432 is formed on dielectric sheet 420 at the oppositeposition to a conductive layer (22P) for the power source, which is oneof the conductive layers 22 on core substrate 20. Through-hole 432penetrates high-dielectric sheet 420 and an interlayer insulation layer410 and reaches the top surface of power source conductive layer (22P).Deeper through-hole 432 is formed before shallower through-hole 431 isformed. Each depth is adjusted by varying the number of laser shots.Specifically, through-hole 432 is formed by using a UV laser (made byHitachi Via Mechanics, Ltd.) under conditions calling for power outputof 3-10 W, frequency of 25-60 kHz, and number of shots 62; through-hole431 is formed under the same conditions, except the number of shots is22. After through-holes 431 and 432 are formed, they are filled withthrough-hole filler resin. The filler resins become inner-hole resins433 and 434 after being dried for an hour at 80° C., for an hour at 120°C., then for 30 minutes at 150° C. (see FIG. 4( d)). The filler resinsto fill the through-holes are prepared as follows: 100 parts by weightof bisphenol-F epoxy monomer (made by Japan Epoxy Resins, Co., Ltd.,molecular amount: 310, product name: E-807) are mixed with 6 parts byweight of imidazole hardening agent (made by Shikoku ChemicalsCorporation, product name: 2E4MZ-CN). Then, 170 parts by weight ofspherical particles SiO₂ with an average particle diameter of 1.6 μm areadded to the mixture, and the viscosity of the mixture is adjusted to45000-49000 cps at a temperature of 23±1° C. by kneading the mixtureusing three rollers.

FIGS. 6( a) and 6(b) illustrate the production of multilayered PCB 10,following the steps shown in FIGS. 4( a)-4(d). Referring to FIGS. 6( a)and 6(b), through-holes 435 and 436 are formed respectively ininner-hole resins 433 and 434 and immersed in a potassium permanganatesolution to roughen the surface, then dry set for three hours at 170° C.until completely set (see FIG. 6( a)). The diameter of through-hole 435is smaller than that of inner-hole resin 433, and through-hole 435penetrates nickel foil 421 and interlayer insulation layer 410 andreaches the top surface of conductive layer (22G). The diameter ofthrough-hole 436 is smaller than that of inner-hole resin 434, andthrough-hole 436 penetrates inner-hole resin 434 and reaches the topsurface of conductive layer (22P). Through-hole 435 is formed by using aUV laser under conditions calling for 25 kHz frequency, 3 W power outputand 52 shots. Through-hole 436 is formed by applying a CO₂ laser beamthrough a Φ1.4 mm mask under conditions of energy density 2.0 mj, pulsewidth 20 μsec. and 2 shots. After a catalyst for electroless copperplating is applied on its surface, the substrate is immersed in a copperplating solution and an electroless copper-plated film 440 is formed onthe substrate. The thickness of the plated film 440 is in the range of0.6-3.0 μm (see FIG. 6( b)). The composition of the electroless copperplating solution for the above procedure is as follows: copper sulfate:0.03 mol/L, EDTA: 0.200 mol/L, HCHO: 0.1 g/L, NaOH: 0.1 mol/L,α,α′-bipyridyl: 100 mg/L, polyethylene glycol (PEG): 0.1 g/L.

FIGS. 7( a)-7(d) illustrate the production of multilayered PCB 10,following the steps shown in FIGS. 6( a) and 6(b). Referring to FIGS. 7(a)-7(d), a dry film is attached onto electroless copper-plated film 440,exposed to light and developed to form a doughnut-shaped plating resist441 surrounding the opening of through-hole 435 (see FIG. 7( a)). On thearea except where the plating resist 441 is located, a 25 μm-thickelectrolytic plating film 442 is formed on electroless copper-platedfilm 440 (see FIG. 7( b)). Accordingly, the inner portion ofthrough-holes 435 and 436 plated with copper becomes via-hole conductors437 and 438, respectively. The composition of the electrolytic copperplating solution for the above procedure is as follows: sulfuric acid:200 g/L, copper sulfate: 80 g/L, additive: 19.5 ml/L (made by AtotechJapan, product name CUPRACID GL). In one example, the electrolyticcopper plating is performed for 115 minutes at a current density of 1A/dm² and a temperature of 23±2° C. After plating resist 441 is peeledoff, a part of electroless copper plating film 440 covered by the resist441 is removed by an etching process using a sulfuric acid-hydrogenperoxide type etching solution (quick etching, see FIG. 7( d)). By theseprocedures, via-hole conductor 437 becomes electrically disconnectedfrom copper foil 422, and thin-film capacitor 40 is formed on coresubstrate 20. Namely, the nickel foil 421 becomes lower electrode 41,high-dielectric layer 423 becomes high-dielectric layer 43, and portionsof copper foil 422, electroless copper plating film 440 and electrolyticcopper film 442, all of which are positioned above high-dielectric layer423, become upper electrode 42. Also, via-hole conductor 437 becomeslower via-hole conductor 45 and via-hole conductor 438 becomes uppervia-hole conductor 48.

FIGS. 8( a)-8(c) illustrate the production of multilayered PCB 10,following the steps shown in FIGS. 7( a)-7(d). Referring to FIGS. 8(a)-8(c), electrolytic copper plating film 442, formed on the unfinishedsubstrate, is treated in a blackening bath (oxidation bath;) using asolution which includes NaOH (10 g/L), NaClO₂ (40 g/L), and Na₃PO₄ (6g/L), and in a reduction bath using a solution which contains NaOH (10g/L) and NaBH₄ (6 g/L), to form a roughened surface on electrolyticcopper plating film 442 (not shown in the drawing). Then, a resininsulation sheet 480 is attached to the roughened surface by using avacuum laminator under conditions calling for a temperature in the rangeof 50-150° C. and a pressure in the range of 0.5-1.5 MPa, and thenhardened for three hours at 150° C. (see FIG. 8( a)). This resininsulation sheet 480 may be denatured epoxy type resin sheet,polyphenylene ether type resin sheet, polyimide type resin sheet, cyanoester type resin sheet or imide type resin sheet. The resin sheet mayinclude thermoplastic resins such as polyolefin type resin or polyimidetype resin, thermosetting resins such as silicone resin, and/or rubbertype resins such as SBR, NBR, or urethane, and may also contain fiber-,filler- or flat-shaped inorganic materials such as silica, alumina orzirconia dispersed therein. Then, a hole 482 is formed at apredetermined position of resin insulation sheet 480 by using a CO₂laser (see FIG. 8( b)). After performing a roughening process andelectroless copper plating, a plating resist is provided on the surface,exposed to light, and developed to form a resist pattern. Next,electrolytic copper plating is performed according to the pattern, andthe plating resist is removed thereafter. Then, portions of electrolesscopper-plated film covered by the plating resist are removed by etchingand BU conductive layer 32 is formed (see FIG. 8( c)). The resininsulation sheet 480 shown in FIG. 8( c) becomes BU insulation layer 36,and the plating inside the hole 482 becomes via-hole conductor 34. Byrepeating the steps of FIGS. 8( a)-8(c), BU part 30 (see FIG. 2) isproduced. Ground pads 61, power source pads 62 and signal pads 63 areformed on the topmost layer of BU part 30, and the multilayered PCB 10shown in FIGS. 1 and 2 is obtained.

According to the present embodiment, during the production ofhigh-dielectric sheet 420, which is to become thin-film capacitor 40, ifpits occur in first sputter film (423 a), the sol-gel solution seepsinto the pits and fills them up. Also, second sputter film (423 c) isformed on intermediate layer (423 b) in high-dielectric layer 423. Evenif pits occur in second sputter film (423 c), they will be smaller andshallower, since second sputter film (423 c) is thinner in the presentembodiment, compared to the case where a high dielectric layer is madeof a single sputter film. Namely, in high-dielectric layer 423, if pitsoccur on the surface opposite to nickel foil 421, they are smaller andshallower than pits that are produced in a high-dielectric layer made ofa single sputter film. Therefore, even if foreign materials (resins ormetals such as copper) enter the pits, they will not cause a majorproblem. Furthermore, intermediate layer (423 b) is sandwiched betweenfirst and second sputter films (423 a) and (423 c), and thus is notexposed. As such, even if pinholes are formed on the surface ofintermediate layer (423 b), the plating solutions used to form copperfoil 422 do not seep into those holes. Accordingly, occurrence of cracksis more effectively prevented in high-dielectric layer 43 of thin-filmcapacitor 40. Short-circuits between lower electrode 41 and upperelectrode 42 are also prevented.

Moreover, the capacitance of thin-film capacitor 40 is larger, sincehigh-dielectric layer 423 is made thinner, with its thickness rangingfrom 0.4 to 3 μm. Therefore, the device has few sudden falls inelectrical potential of power source caused by high-speed on/offswitching of semiconductor element 70 mounted on multilayered PCB 10.

Further, since the individual thickness of first and second sputterfilms (423 a) and (423 c) is 0.1 μm or greater, the intermediate layer(423 b), sandwiched between first and second sputter films (423 a) and(423 c), is completely isolated from surroundings.

Since intermediate layer (423 b) is also formed thicker than firstsputter film (423 a) and second sputter film (423 c), pits that couldoccur on first and second sputter films (423 a) and (423 c) are evensmaller and shallower and cause much less potential problems. Inaddition, according to the above-mentioned embodiment, second sputterfilm (423 c) is formed thinner than first sputter film (423 a),occurrence of problems are further suppressed.

Furthermore, soon after high-dielectric sheet 420 is produced, low- andhigh-temperature treatments are conducted several times to select asheet that shows no problems and use it in the next production process.By excluding a potentially problematic sheet before mounting it on amultilayered PCB 10, the cost is significantly reduced, compared tohaving to remove one after it is mounted.

According to the above-described embodiment, thin-film capacitor 40 isformed on core substrate 20, and build-up part 30 is formed on thin-filmcapacitor 40. However, build-up part 30 may be formed on core substrate20 and then thin-film capacitor 40 on top of build-up part 30.

In the above-described embodiment, nickel is used to form lowerelectrode 41. However, copper, platinum, gold or silver may be usedinstead. Also, copper is used to form upper electrode 42, but othermetals such as nickel and tin may be used.

Furthermore, a magnetron sputtering apparatus is used in the sputteringprocess in the above-described method, but a tri-polar or ion-beamsputtering apparatus may be used.

In the above-described embodiment, the cross-section of BU via-holeconductor 34 is formed in a tumbler shape (what is called a conformalvia-hole), but it may also be a filled-type via-hole, which is atumbler-shaped hole filled with a metal or conductive resin.

EXAMPLES

Table 1 shows multilayered PCBs 10 of Examples 1-8 prepared by theabove-described method of producing high-dielectric sheet 420 andmultilayered PCB 10 according to the present embodiment. For the purposeof comparison, multilayered PCBs of Comparative Examples 1-2 were alsoproduced and evaluated. The first sputter film, intermediate layer andsecond sputter film of the high-dielectric sheets in Examples 1-8 andComparative Examples 1-2 are all made of barium titanate.

<Percentage of Evaluated Products That Passed the Test>

In Examples 1-8 and Comparative Examples 1-2, 100 multilayered PCBs 10per example were produced and their connectivity was tested. Inconnectivity tests explained below referring to FIG. 9, the followinglines were checked if they were disconnected: (1) ground line 71connecting each ground pad 61 of mounting part 60 to the correspondingexternal ground terminal 81, which is located on the surface opposite tomounting part 60, via lower electrode 41 of thin-film capacitor 40; (2)power source line 72 connecting each power source pad 62 of mountingpart 60 to the corresponding external power source terminal 82, viaupper electrode 42 of thin-film capacitor 40; and (3) multiple signallines 73 connecting each signal pad 63 to the corresponding externalsignal terminals 83 without making contact with lower electrode 41 orupper electrode 42.

Also, tests were conducted to determine whether short-circuiting occursamong the ground line 71, power source line 72 and signal lines 73. Theevaluated multilayered PCBs 10 passed the test if all the lines showedno sign of disconnection or short-circuits, but it failed if at leastone line showed any sign of disconnection or short-circuits. Among 100multilayered PCBs 10 tested in each category, the number that passed isshown in percentages in Table 1.

<Reliability Test 1>

For each of Examples 1-8, reliability tests were conducted as follows.Several ground pads 61 were selected from numerous ground pads 61 formedon mounting part 60 of multilayered PCB 10, and the electricalresistance value between the ground pads 61 and the correspondingexternal ground terminal 81 was measured. Also, several power supplypads 62 on mounting part 60 were selected, and the electricityresistance value between the power supply pads 62 and the correspondingexternal power supply terminal 82 was also measured. Each result wasrecorded as an initial value (R0). Next, voltage of 3.3 volts wasapplied between upper electrode 42 and lower electrode 41 of thin-filmcapacitor 40, and the capacitor 40 was charged and then discharged. Theprocess of charging and discharging was repeated 50 times. Then, a heatcycle test, in which multilayered PCB 10 was left at −55° C. for 5minutes and at 125° C. for 5 minutes, was repeated 500 times. Afterthese tests, measurements were made of connection resistance values (R)between pads and corresponding external terminals, where initial values(R0) were measured earlier. From the (R) value obtained between each padand its corresponding external terminal, each initial value (R0) wassubtracted, divided by the (R0) and multiplied by 100 (100×(R−R0)/R0)(%). If all the values obtained were within the range of ±10%, theExample passed the reliability test. If not, it failed. The results areshown in Table 1. The multilayered PCBs 10 in the tested Examples andComparative Examples each have basically the same structures as shown inFIGS. 1 and 2, having common material, size and position of each partremaining constant, and differing only in parameters provided in Table1.

<Reliability Test 2>

Except that the number of test times of charging and discharging was100, and the number of repeated heat cycle tests was 1,000, all otherconditions were the same as the Reliability Test 1. The results areshown in Table 1.

TABLE 1 thickness thickness thickness test (μm) (μm) (μm) total passingreliability 1st sputter intermediate 2nd sputter thickness rate testExamples film layer film (μm) (%) 1 2 Example 1 0.25 0.3 0.15 0.7 100Pass Pass Example 2 1 1.4 0.6 3 100 Pass Pass Example 3 0.1 0.2 0.1 0.4100 Pass Fail Example 4 0.2 0.3 0.2 0.7 100 Pass Fail Example 5 0.250.35 0.25 0.85 100 Pass Fail Example 6 0.5 0.55 0.5 1.55 100 Pass FailExample 7 0.6 0.8 0.6 2 100 Pass Fail Example 8 0.8 1.4 0.8 3 100 PassFail Comparative 0.85 0 0 0.85 30 — — Example 1 Comparative 0 0.85 00.85 20 — — Example 2

As clearly shown in Table 1, only 20 percent of the evaluatedmultilayered PCBs 10 passed the test in Comparative Example 1, and 30percent in Comparative Example 2, whereas 100 percent passed in Examples1-8. In Comparative Example 1, high-dielectric layer 423 ofhigh-dielectric sheet 420 consists of a single sputter film only, and inComparative Example 2, it is made of only an intermediate layer formedby calcining a sol-gel film, whereas in Examples 1-8, eachhigh-dielectric layer 423 has a three-layer structure of first sputterfilm (423 a)/intermediate layer (423 b)/second sputter film (423 c).When high-dielectric layer 423 was comprised of a sputter film alone,large, deep pits occurred on the surface. Those pits appeared to becomethe starting points of problem-causing cracks, thereby lowering thepassing rate. When high-dielectric layer 423 was made of an intermediatelayer only, it seemed that pinholes occurred where organic materials andsolvents decomposed or evaporated, and plating solutions seeped intothose pinholes, potentially causing short-circuits, thereby lowering thepassing rate. Compared with those Comparative Examples, in Examples 1-8,even if pits occurred on the surface of high-dielectric layer 423, theywere likely to be smaller and shallower, since second sputter film (423c) was thinner. Thus, cracks starting from pinholes were seeminglyprevented. Intermediate layer (423 b) was sandwiched between firstsputter film (423 a) and second sputter film (423 c), and was notexposed. Even if pinholes occurred in intermediate layer (423 b),plating solutions could not seep into those pinholes, thusshort-circuits were seemingly prevented. Other factors related to theexcellent passing rates seem to be that the total thickness ofhigh-dielectric layer 423 was in the range of 0.4-3 μm, thatintermediate layer (423 b) was thicker than both first sputter film (423a) and second sputter film (423 c), and that intermediate layer (423 b)was completely insulated by making the thicknesses of first and secondsputter films (423 a) and (423 c) each 0.1 μm or greater.

In Reliability Test 1, Examples 1-8 all had good results, but inReliability Test 2, only Examples 1 and 2 fared well. The reasons forthis may be related to the fact that the pits that occurred on thesurface of second sputter film (423 c) were small and shallow becausesecond sputter film (423 c) was formed thinner than first sputter film(423 a).

As discussed above, in a method to produce a high-dielectric sheet usedas a thin-film capacitor provided inside a PCB, according to the aboveembodiment of the present invention, a high-dielectric layer is providedon a first electrode by forming, layer by layer, a first sputter film byusing a sputtering process, a sol-gel film by using a sol-gel process,and a second sputter film by using a sputtering process, and an oppositeelectrode facing the first electrode is provided on the second sputterfilm.

According to the above-described method, if pits occur when the firstsputter film is formed, they will be filled when a sol-gel film isformed onto the first sputter film and the sol-gel solution seeps intothem. The second sputter film, formed on the sol-gel film, is thinnerthan that of a high-dielectric layer comprised only of a single sputterfilm. Thus, even if pits occur on the second sputter film, they aresmaller and shallower and if foreign materials (such as metal or resin)seep into the pits, they will not cause a major problem. Furthermore,since the sol-gel film is sandwiched between the first and secondsputter films, if pinholes occur, any plating solutions or etchants thatmight be around the high-dielectric layer will not seep into thosepinholes. Therefore, according to the method of the present embodiment,cracks in the high-dielectric layer are prevented, and short-circuitsbetween the opposing electrodes are also prevented.

In the production method of a high-dielectric sheet according to thepresent embodiment, the thickness of the high-dielectric layer ispreferably in the range of 0.4-3 μm. If the thickness is within thatrange, the capacitance of the high-dielectric sheet is high enough toeffectively prevent a sudden drop in electrical potential caused byswitching on/off the semiconductor element mounted on the PCB at a highspeed. If the high-dielectric layer is thinner than the above range, therisk of cracks developing in the high-dielectric layer or ofshort-circuits occurring between the opposing electrodes may be higher.Thus, employing the production method of the present embodiment isadvantageous in eliminating the risk.

In the production method of a high-dielectric sheet according to thepresent embodiment, the thickness of each sputter film is preferably 0.1μm or greater. If the thickness is in that range, the sol-gel filmsandwiched between the first and second sputter films is well isolatedfrom surroundings.

In the production method of a high-dielectric sheet according to thepresent embodiment, the sol-gel film is preferably thicker than thefirst and second sputter films. If the sol-gel film is thicker, pitsoccurring in the first and second sputter films will be even smaller andshallower than otherwise, and problems caused by pits may occur lessfrequently. Further, the above-mentioned second sputter film should bepreferably thinner than the above-mentioned first sputter film.

In the production method of a high-dielectric sheet according to thepresent embodiment, after an opposing electrode is formed,high-dielectric sheets having a high-dielectric layer sandwiched betweenthe opposing electrodes are subjected to lower-temperature treatment andhigher-temperature treatment multiple times, and ones that aresubstantially free from defects are selected. Through this selectionprocess, a defective high-dielectric sheet is excluded before it isincorporated into a PCB. This method is less costly than removing adefective sheet after it is already positioned on the board. During theabove lower-temperature process, the sheet is left for a predeterminedperiod of time at 0° C. or lower, and during the abovehigher-temperature process for a predetermined period of time at 100° C.or higher.

Throughout this specification, descriptions are made by using terms suchas “top” and “bottom” for ease of explanation of the positionalrelationships of the structural elements. However, structures are notlimited to those described above, that is, positions may be upside down,and right and left may be reversed.

Obviously, numerous modifications and variations of the presentinvention are possible in light of the above teachings. It is thereforeto be understood that within the scope of the appended claims, theinvention may be practiced otherwise than as specifically describedherein.

1. A method of producing a capacitor for a printed circuit board,comprising: producing a plurality of high-dielectric sheets, each of theplurality of high-dielectric sheets being produced by providing a firstelectrode, forming a first sputter film on the first electrode, formingan intermediate layer on the first sputter film by calcining a sol-gelfilm, forming a second sputter film on the intermediate layer, andproviding a second electrode on the second sputter film; and subjectingthe plurality of high-dielectric sheets to a heat process in which thehigh-dielectric sheets are subjected to a first temperature at leastonce and a second temperature higher than the first temperature at leastonce; and selecting ones of the plurality of high-dielectric sheets,which are substantially free from a defect after the heat process. 2.The method according to claim 1, wherein the first temperature is 0° C.or lower.
 3. The method according to claim 1, wherein the secondtemperature is 100° C. or higher.
 4. A high-dielectric sheet for aprinted circuit board, comprising: a first electrode; a first sputterfilm formed on the first electrode; an intermediate layer formed on thefirst sputter film by calcining a sol-gel film; a second sputter filmformed on the intermediate layer; and a second electrode provided on thesecond sputter film.
 5. The sheet according to claim 4, wherein thefirst sputter film, the intermediate layer and the second sputter filmhave a total thickness in the range between 0.4 and 3 μm.
 6. The sheetaccording to claim 4, wherein the first sputter film has a thickness of0.1 μm or greater.
 7. The sheet according to claim 4, wherein the secondsputter film has a thickness of 0.1 μm or greater.
 8. The sheetaccording to claim 4, wherein the intermediate layer is thicker than thefirst and second sputter films.
 9. The sheet according to claim 4,wherein the second sputter film is thinner than the first sputter film.10. The sheet according to claim 4, wherein the first sputter film, theintermediate layer and the second sputter film comprise at least onematerial selected from the group consisting of barium titanate, SrTiO₃,TaO₃, Ta₂O₅, lead zirconate titanate, lead lanthanum zirconate titanate,lead niobium zirconate titanate, lead calcium zirconate titanate andlead strontium zirconate titanate.
 11. The sheet according to claim 4,wherein the first electrode comprises a material selected from the groupconsisting of nickel, copper, platinum, gold and silver.
 12. The sheetaccording to claim 4, wherein the second electrode comprises a materialselected from the group consisting of copper, nickel and tin.
 13. Aprinted circuit board comprising: a core substrate; and a capacitorpositioned over the core substrate, the capacitor having a firstelectrode, a first sputter film formed on the first electrode, anintermediate layer formed on the first sputter film by calcining asol-gel film, a second sputter film formed on the intermediate layer,and a second electrode provided on the second sputter film.